(pcb /home/ixyd/Nextcloud/funkstuff/projects/antennaswitch/electronics/first_try.dsn
  (parser
    (string_quote ")
    (space_in_quoted_tokens on)
    (host_cad "KiCad's Pcbnew")
    (host_version "5.1.9+dfsg1-1")
  )
  (resolution um 10)
  (unit um)
  (structure
    (layer F.Cu
      (type signal)
      (property
        (index 0)
      )
    )
    (layer B.Cu
      (type signal)
      (property
        (index 1)
      )
    )
    (boundary
      (path pcb 0  230000 -144000  67000 -144000  67000 -32000  230000 -32000
            230000 -144000)
    )
    (plane GND (polygon B.Cu 0  229000 -143000  68000 -143000  68000 -33000  229000 -33000
            229000 -143000))
    (plane VCC (polygon F.Cu 0  229000 -143000  68000 -143000  68000 -33000  229000 -33000
            229000 -143000))
    (via "Via[0-1]_800:400_um" "Via[0-1]_1000:400_um" "Via[0-1]_1500:400_um")
    (rule
      (width 250)
      (clearance 400.1)
      (clearance 400.1 (type default_smd))
      (clearance 100 (type smd_smd))
    )
  )
  (placement
    (component first_try:my_pl_socket
      (place J_IN3 137000 -41000 front 0 (PN Conn_Coaxial))
      (place J_OUT1 163000 -41000 front 0 (PN Conn_Coaxial))
      (place J_IN2 111000 -41000 front 0 (PN Conn_Coaxial))
      (place J_OUT3 215000 -41000 front 0 (PN Conn_Coaxial))
      (place J_IN1 83000 -41000 front 0 (PN Conn_Coaxial))
    )
    (component "Package_DIP:DIP-16_W7.62mm_Socket"
      (place U1 143096 -105662 front 90 (PN ULN2003A))
    )
    (component Module:Arduino_Nano
      (place A1 168496 -111758 front 270 (PN Arduino_Nano_Every))
    )
    (component MountingHole:MountingHole_3.2mm_M3_DIN965_Pad
      (place H1 73000 -51000 front 0 (PN MountingHole))
      (place H3 75000 -136000 front 0 (PN MountingHole))
    )
    (component MountingHole:MountingHole_3.2mm_M3_DIN965_Pad::1
      (place H2 223000 -136000 front 0 (PN MountingHole))
      (place H4 223000 -50000 front 0 (PN MountingHole))
    )
    (component "Connector_Wire:SolderWire-0.5sqmm_1x02_P4.6mm_D0.9mm_OD2.1mm"
      (place J1 217500 -112000 front 270 (PN Conn_01x02_Male))
    )
    (component Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical
      (place J2 150716 -133888 front 90 (PN "I2C Display"))
    )
    (component first_try:my_pl_socket::1
      (place J_OUT2 189000 -41000 front 0 (PN Conn_Coaxial))
    )
    (component Capacitor_THT:CP_Radial_D4.0mm_P2.00mm
      (place C1 207500 -119500 front 270 (PN 0,22µF))
    )
    (component Capacitor_THT:CP_Radial_D4.0mm_P2.00mm::1
      (place C2 200000 -119500 front 270 (PN 0,22µF))
    )
    (component "Package_TO_SOT_THT:TO-220-3_Vertical"
      (place U2 201000 -112300 front 0 (PN LM7805_TO220))
    )
    (component Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal
      (place R1 187500 -104500 front 0 (PN 100k))
    )
    (component Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical
      (place SW1 180000 -107000 front 180 (PN SW_Push))
    )
    (component st1:ST1DC12VF
      (place K1 75000 -60000 front 270 (PN "ST1-DC12V-F"))
      (place K2 154000 -60000 front 270 (PN "ST1-DC12V-F"))
      (place K4 180000 -60000 front 270 (PN "ST1-DC12V-F"))
    )
    (component st1:ST1DC12VF::1
      (place K3 103000 -60000 front 270 (PN "ST1-DC12V-F"))
      (place K5 129000 -60000 front 270 (PN "ST1-DC12V-F"))
      (place K6 206000 -60000 front 270 (PN "ST1-DC12V-F"))
    )
  )
  (library
    (image first_try:my_pl_socket
      (outline (path signal 120  11430 -5080  11430 6350))
      (outline (path signal 120  11430 6350  -12700 6350))
      (outline (path signal 120  -12700 6350  -12700 -5080))
      (outline (path signal 120  -12700 -5080  11430 -5080))
      (pin Round[A]Pad_4000_um 2 -8890 0)
      (pin Round[A]Pad_4000_um 1 0 0)
    )
    (image "Package_DIP:DIP-16_W7.62mm_Socket"
      (outline (path signal 100  1635 1270  6985 1270))
      (outline (path signal 100  6985 1270  6985 -19050))
      (outline (path signal 100  6985 -19050  635 -19050))
      (outline (path signal 100  635 -19050  635 270))
      (outline (path signal 100  635 270  1635 1270))
      (outline (path signal 100  -1270 1330  -1270 -19110))
      (outline (path signal 100  -1270 -19110  8890 -19110))
      (outline (path signal 100  8890 -19110  8890 1330))
      (outline (path signal 100  8890 1330  -1270 1330))
      (outline (path signal 120  2810 1330  1160 1330))
      (outline (path signal 120  1160 1330  1160 -19110))
      (outline (path signal 120  1160 -19110  6460 -19110))
      (outline (path signal 120  6460 -19110  6460 1330))
      (outline (path signal 120  6460 1330  4810 1330))
      (outline (path signal 120  -1330 1390  -1330 -19170))
      (outline (path signal 120  -1330 -19170  8950 -19170))
      (outline (path signal 120  8950 -19170  8950 1390))
      (outline (path signal 120  8950 1390  -1330 1390))
      (outline (path signal 50  -1550 1600  -1550 -19400))
      (outline (path signal 50  -1550 -19400  9150 -19400))
      (outline (path signal 50  9150 -19400  9150 1600))
      (outline (path signal 50  9150 1600  -1550 1600))
      (pin Oval[A]Pad_1600x1600_um 16 7620 0)
      (pin Oval[A]Pad_1600x1600_um 8 0 -17780)
      (pin Oval[A]Pad_1600x1600_um 15 7620 -2540)
      (pin Oval[A]Pad_1600x1600_um 7 0 -15240)
      (pin Oval[A]Pad_1600x1600_um 14 7620 -5080)
      (pin Oval[A]Pad_1600x1600_um 6 0 -12700)
      (pin Oval[A]Pad_1600x1600_um 13 7620 -7620)
      (pin Oval[A]Pad_1600x1600_um 5 0 -10160)
      (pin Oval[A]Pad_1600x1600_um 12 7620 -10160)
      (pin Oval[A]Pad_1600x1600_um 4 0 -7620)
      (pin Oval[A]Pad_1600x1600_um 11 7620 -12700)
      (pin Oval[A]Pad_1600x1600_um 3 0 -5080)
      (pin Oval[A]Pad_1600x1600_um 10 7620 -15240)
      (pin Oval[A]Pad_1600x1600_um 2 0 -2540)
      (pin Oval[A]Pad_1600x1600_um 9 7620 -17780)
      (pin Rect[A]Pad_1600x1600_um 1 0 0)
    )
    (image Module:Arduino_Nano
      (outline (path signal 120  1270 -1270  1270 1270))
      (outline (path signal 120  1270 1270  -1400 1270))
      (outline (path signal 120  -1400 -1270  -1400 -39500))
      (outline (path signal 120  -1400 3940  -1400 1270))
      (outline (path signal 120  13970 1270  16640 1270))
      (outline (path signal 120  13970 1270  13970 -36830))
      (outline (path signal 120  13970 -36830  16640 -36830))
      (outline (path signal 120  1270 -1270  -1400 -1270))
      (outline (path signal 120  1270 -1270  1270 -36830))
      (outline (path signal 120  1270 -36830  -1400 -36830))
      (outline (path signal 100  3810 -31750  11430 -31750))
      (outline (path signal 100  11430 -31750  11430 -41910))
      (outline (path signal 100  11430 -41910  3810 -41910))
      (outline (path signal 100  3810 -41910  3810 -31750))
      (outline (path signal 120  -1400 -39500  16640 -39500))
      (outline (path signal 120  16640 -39500  16640 3940))
      (outline (path signal 120  16640 3940  -1400 3940))
      (outline (path signal 100  16510 -39370  -1270 -39370))
      (outline (path signal 100  -1270 -39370  -1270 2540))
      (outline (path signal 100  -1270 2540  0 3810))
      (outline (path signal 100  0 3810  16510 3810))
      (outline (path signal 100  16510 3810  16510 -39370))
      (outline (path signal 50  -1530 4060  16750 4060))
      (outline (path signal 50  -1530 4060  -1530 -42160))
      (outline (path signal 50  16750 -42160  16750 4060))
      (outline (path signal 50  16750 -42160  -1530 -42160))
      (pin Oval[A]Pad_1600x1600_um 16 15240 -35560)
      (pin Oval[A]Pad_1600x1600_um 15 0 -35560)
      (pin Oval[A]Pad_1600x1600_um 30 15240 0)
      (pin Oval[A]Pad_1600x1600_um 14 0 -33020)
      (pin Oval[A]Pad_1600x1600_um 29 15240 -2540)
      (pin Oval[A]Pad_1600x1600_um 13 0 -30480)
      (pin Oval[A]Pad_1600x1600_um 28 15240 -5080)
      (pin Oval[A]Pad_1600x1600_um 12 0 -27940)
      (pin Oval[A]Pad_1600x1600_um 27 15240 -7620)
      (pin Oval[A]Pad_1600x1600_um 11 0 -25400)
      (pin Oval[A]Pad_1600x1600_um 26 15240 -10160)
      (pin Oval[A]Pad_1600x1600_um 10 0 -22860)
      (pin Oval[A]Pad_1600x1600_um 25 15240 -12700)
      (pin Oval[A]Pad_1600x1600_um 9 0 -20320)
      (pin Oval[A]Pad_1600x1600_um 24 15240 -15240)
      (pin Oval[A]Pad_1600x1600_um 8 0 -17780)
      (pin Oval[A]Pad_1600x1600_um 23 15240 -17780)
      (pin Oval[A]Pad_1600x1600_um 7 0 -15240)
      (pin Oval[A]Pad_1600x1600_um 22 15240 -20320)
      (pin Oval[A]Pad_1600x1600_um 6 0 -12700)
      (pin Oval[A]Pad_1600x1600_um 21 15240 -22860)
      (pin Oval[A]Pad_1600x1600_um 5 0 -10160)
      (pin Oval[A]Pad_1600x1600_um 20 15240 -25400)
      (pin Oval[A]Pad_1600x1600_um 4 0 -7620)
      (pin Oval[A]Pad_1600x1600_um 19 15240 -27940)
      (pin Oval[A]Pad_1600x1600_um 3 0 -5080)
      (pin Oval[A]Pad_1600x1600_um 18 15240 -30480)
      (pin Oval[A]Pad_1600x1600_um 2 0 -2540)
      (pin Oval[A]Pad_1600x1600_um 17 15240 -33020)
      (pin Rect[A]Pad_1600x1600_um 1 0 0)
    )
    (image MountingHole:MountingHole_3.2mm_M3_DIN965_Pad
      (outline (path signal 50  3050 0  2967.79 -703.378  2725.58 -1368.84  2336.44 -1960.5
            1821.33 -2446.48  1208.04 -2800.56  529.627 -3003.66  -177.342 -3044.84
            -874.75 -2921.87  -1525 -2641.38  -2093.04 -2218.49  -2548.24 -1676
            -2866.06 -1043.16  -3029.38 -354.083  -3029.38 354.083  -2866.06 1043.16
            -2548.24 1676  -2093.04 2218.49  -1525 2641.38  -874.75 2921.87
            -177.342 3044.84  529.627 3003.66  1208.04 2800.56  1821.33 2446.48
            2336.44 1960.5  2725.58 1368.84  2967.79 703.378  3050 0))
      (outline (path signal 150  2800 0  2718.64 -670.084  2479.28 -1301.22  2095.83 -1856.74
            1590.58 -2304.36  992.894 -2618.05  337.503 -2779.59  -337.503 -2779.59
            -992.894 -2618.05  -1590.58 -2304.36  -2095.83 -1856.74  -2479.28 -1301.22
            -2718.64 -670.084  -2800 0  -2718.64 670.084  -2479.28 1301.22
            -2095.83 1856.74  -1590.58 2304.36  -992.894 2618.05  -337.503 2779.59
            337.503 2779.59  992.894 2618.05  1590.58 2304.36  2095.83 1856.74
            2479.28 1301.22  2718.64 670.084  2800 0))
      (pin Round[A]Pad_5600_um 1 0 0)
    )
    (image MountingHole:MountingHole_3.2mm_M3_DIN965_Pad::1
      (outline (path signal 150  2800 0  2718.64 -670.084  2479.28 -1301.22  2095.83 -1856.74
            1590.58 -2304.36  992.894 -2618.05  337.503 -2779.59  -337.503 -2779.59
            -992.894 -2618.05  -1590.58 -2304.36  -2095.83 -1856.74  -2479.28 -1301.22
            -2718.64 -670.084  -2800 0  -2718.64 670.084  -2479.28 1301.22
            -2095.83 1856.74  -1590.58 2304.36  -992.894 2618.05  -337.503 2779.59
            337.503 2779.59  992.894 2618.05  1590.58 2304.36  2095.83 1856.74
            2479.28 1301.22  2718.64 670.084  2800 0))
      (outline (path signal 50  3050 0  2967.79 -703.378  2725.58 -1368.84  2336.44 -1960.5
            1821.33 -2446.48  1208.04 -2800.56  529.627 -3003.66  -177.342 -3044.84
            -874.75 -2921.87  -1525 -2641.38  -2093.04 -2218.49  -2548.24 -1676
            -2866.06 -1043.16  -3029.38 -354.083  -3029.38 354.083  -2866.06 1043.16
            -2548.24 1676  -2093.04 2218.49  -1525 2641.38  -874.75 2921.87
            -177.342 3044.84  529.627 3003.66  1208.04 2800.56  1821.33 2446.48
            2336.44 1960.5  2725.58 1368.84  2967.79 703.378  3050 0))
      (pin Round[A]Pad_5600_um 1 0 0)
    )
    (image "Connector_Wire:SolderWire-0.5sqmm_1x02_P4.6mm_D0.9mm_OD2.1mm"
      (outline (path signal 100  1050 0  970.074 -401.818  742.462 -742.462  401.818 -970.074
            0 -1050  -401.818 -970.074  -742.462 -742.462  -970.074 -401.818
            -1050 0  -970.074 401.818  -742.462 742.462  -401.818 970.074
            0 1050  401.818 970.074  742.462 742.462  970.074 401.818  1050 0))
      (outline (path signal 100  5650 0  5570.07 -401.818  5342.46 -742.462  5001.82 -970.074
            4600 -1050  4198.18 -970.074  3857.54 -742.462  3629.93 -401.818
            3550 0  3629.93 401.818  3857.54 742.462  4198.18 970.074  4600 1050
            5001.82 970.074  5342.46 742.462  5570.07 401.818  5650 0))
      (outline (path signal 50  -1800 1550  -1800 -1550))
      (outline (path signal 50  -1800 -1550  1800 -1550))
      (outline (path signal 50  1800 -1550  1800 1550))
      (outline (path signal 50  1800 1550  -1800 1550))
      (outline (path signal 50  2800 1550  2800 -1550))
      (outline (path signal 50  2800 -1550  6400 -1550))
      (outline (path signal 50  6400 -1550  6400 1550))
      (outline (path signal 50  6400 1550  2800 1550))
      (pin RoundRect[A]Pad_2100x2100_250.95_um 1 0 0)
      (pin Round[A]Pad_2100_um 2 4600 0)
    )
    (image Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical
      (outline (path signal 100  -635 1270  1270 1270))
      (outline (path signal 100  1270 1270  1270 -8890))
      (outline (path signal 100  1270 -8890  -1270 -8890))
      (outline (path signal 100  -1270 -8890  -1270 635))
      (outline (path signal 100  -1270 635  -635 1270))
      (outline (path signal 120  -1330 -8950  1330 -8950))
      (outline (path signal 120  -1330 -1270  -1330 -8950))
      (outline (path signal 120  1330 -1270  1330 -8950))
      (outline (path signal 120  -1330 -1270  1330 -1270))
      (outline (path signal 120  -1330 0  -1330 1330))
      (outline (path signal 120  -1330 1330  0 1330))
      (outline (path signal 50  -1800 1800  -1800 -9400))
      (outline (path signal 50  -1800 -9400  1800 -9400))
      (outline (path signal 50  1800 -9400  1800 1800))
      (outline (path signal 50  1800 1800  -1800 1800))
      (pin Rect[A]Pad_1700x1700_um 1 0 0)
      (pin Oval[A]Pad_1700x1700_um 2 0 -2540)
      (pin Oval[A]Pad_1700x1700_um 3 0 -5080)
      (pin Oval[A]Pad_1700x1700_um 4 0 -7620)
    )
    (image first_try:my_pl_socket::1
      (outline (path signal 120  11430 -5080  11430 6350))
      (outline (path signal 120  11430 6350  -12700 6350))
      (outline (path signal 120  -12700 6350  -12700 -5080))
      (outline (path signal 120  -12700 -5080  11430 -5080))
      (pin Round[A]Pad_4000_um 1 0 0)
      (pin Round[A]Pad_4000_um 2 -8890 0)
    )
    (image Capacitor_THT:CP_Radial_D4.0mm_P2.00mm
      (outline (path signal 120  -1069.8 1395  -1069.8 995))
      (outline (path signal 120  -1269.8 1195  -869.801 1195))
      (outline (path signal 120  3081 370  3081 -370))
      (outline (path signal 120  3041 537  3041 -537))
      (outline (path signal 120  3001 664  3001 -664))
      (outline (path signal 120  2961 768  2961 -768))
      (outline (path signal 120  2921 859  2921 -859))
      (outline (path signal 120  2881 940  2881 -940))
      (outline (path signal 120  2841 1013  2841 -1013))
      (outline (path signal 120  2801 -840  2801 -1080))
      (outline (path signal 120  2801 1080  2801 840))
      (outline (path signal 120  2761 -840  2761 -1142))
      (outline (path signal 120  2761 1142  2761 840))
      (outline (path signal 120  2721 -840  2721 -1200))
      (outline (path signal 120  2721 1200  2721 840))
      (outline (path signal 120  2681 -840  2681 -1254))
      (outline (path signal 120  2681 1254  2681 840))
      (outline (path signal 120  2641 -840  2641 -1304))
      (outline (path signal 120  2641 1304  2641 840))
      (outline (path signal 120  2601 -840  2601 -1351))
      (outline (path signal 120  2601 1351  2601 840))
      (outline (path signal 120  2561 -840  2561 -1396))
      (outline (path signal 120  2561 1396  2561 840))
      (outline (path signal 120  2521 -840  2521 -1438))
      (outline (path signal 120  2521 1438  2521 840))
      (outline (path signal 120  2481 -840  2481 -1478))
      (outline (path signal 120  2481 1478  2481 840))
      (outline (path signal 120  2441 -840  2441 -1516))
      (outline (path signal 120  2441 1516  2441 840))
      (outline (path signal 120  2401 -840  2401 -1552))
      (outline (path signal 120  2401 1552  2401 840))
      (outline (path signal 120  2361 -840  2361 -1587))
      (outline (path signal 120  2361 1587  2361 840))
      (outline (path signal 120  2321 -840  2321 -1619))
      (outline (path signal 120  2321 1619  2321 840))
      (outline (path signal 120  2281 -840  2281 -1650))
      (outline (path signal 120  2281 1650  2281 840))
      (outline (path signal 120  2241 -840  2241 -1680))
      (outline (path signal 120  2241 1680  2241 840))
      (outline (path signal 120  2201 -840  2201 -1708))
      (outline (path signal 120  2201 1708  2201 840))
      (outline (path signal 120  2161 -840  2161 -1735))
      (outline (path signal 120  2161 1735  2161 840))
      (outline (path signal 120  2121 -840  2121 -1760))
      (outline (path signal 120  2121 1760  2121 840))
      (outline (path signal 120  2081 -840  2081 -1785))
      (outline (path signal 120  2081 1785  2081 840))
      (outline (path signal 120  2041 -840  2041 -1808))
      (outline (path signal 120  2041 1808  2041 840))
      (outline (path signal 120  2001 -840  2001 -1830))
      (outline (path signal 120  2001 1830  2001 840))
      (outline (path signal 120  1961 -840  1961 -1851))
      (outline (path signal 120  1961 1851  1961 840))
      (outline (path signal 120  1921 -840  1921 -1870))
      (outline (path signal 120  1921 1870  1921 840))
      (outline (path signal 120  1881 -840  1881 -1889))
      (outline (path signal 120  1881 1889  1881 840))
      (outline (path signal 120  1841 -840  1841 -1907))
      (outline (path signal 120  1841 1907  1841 840))
      (outline (path signal 120  1801 -840  1801 -1924))
      (outline (path signal 120  1801 1924  1801 840))
      (outline (path signal 120  1761 -840  1761 -1940))
      (outline (path signal 120  1761 1940  1761 840))
      (outline (path signal 120  1721 -840  1721 -1954))
      (outline (path signal 120  1721 1954  1721 840))
      (outline (path signal 120  1680 -840  1680 -1968))
      (outline (path signal 120  1680 1968  1680 840))
      (outline (path signal 120  1640 -840  1640 -1982))
      (outline (path signal 120  1640 1982  1640 840))
      (outline (path signal 120  1600 -840  1600 -1994))
      (outline (path signal 120  1600 1994  1600 840))
      (outline (path signal 120  1560 -840  1560 -2005))
      (outline (path signal 120  1560 2005  1560 840))
      (outline (path signal 120  1520 -840  1520 -2016))
      (outline (path signal 120  1520 2016  1520 840))
      (outline (path signal 120  1480 -840  1480 -2025))
      (outline (path signal 120  1480 2025  1480 840))
      (outline (path signal 120  1440 -840  1440 -2034))
      (outline (path signal 120  1440 2034  1440 840))
      (outline (path signal 120  1400 -840  1400 -2042))
      (outline (path signal 120  1400 2042  1400 840))
      (outline (path signal 120  1360 -840  1360 -2050))
      (outline (path signal 120  1360 2050  1360 840))
      (outline (path signal 120  1320 -840  1320 -2056))
      (outline (path signal 120  1320 2056  1320 840))
      (outline (path signal 120  1280 -840  1280 -2062))
      (outline (path signal 120  1280 2062  1280 840))
      (outline (path signal 120  1240 -840  1240 -2067))
      (outline (path signal 120  1240 2067  1240 840))
      (outline (path signal 120  1200 -840  1200 -2071))
      (outline (path signal 120  1200 2071  1200 840))
      (outline (path signal 120  1160 2074  1160 -2074))
      (outline (path signal 120  1120 2077  1120 -2077))
      (outline (path signal 120  1080 2079  1080 -2079))
      (outline (path signal 120  1040 2080  1040 -2080))
      (outline (path signal 120  1000 2080  1000 -2080))
      (outline (path signal 100  -502.554 1067.5  -502.554 667.5))
      (outline (path signal 100  -702.554 867.5  -302.554 867.5))
      (outline (path signal 50  3250 0  3173.33 -582.343  2948.56 -1125  2590.99 -1590.99
            2125 -1948.56  1582.34 -2173.33  1000 -2250  417.657 -2173.33
            -125 -1948.56  -590.99 -1590.99  -948.557 -1125  -1173.33 -582.343
            -1250 0  -1173.33 582.343  -948.557 1125  -590.99 1590.99  -125 1948.56
            417.657 2173.33  1000 2250  1582.34 2173.33  2125 1948.56  2590.99 1590.99
            2948.56 1125  3173.33 582.343  3250 0))
      (outline (path signal 120  3120 0  3041.39 -571.969  2811.37 -1101.52  2447.01 -1549.37
            1975.34 -1882.32  1431.33 -2075.66  855.326 -2115.06  290.055 -1997.59
            -222.562 -1731.98  -644.508 -1337.91  -944.488 -844.61  -1100.25 -288.673
            -1100.25 288.673  -944.488 844.61  -644.508 1337.91  -222.562 1731.98
            290.055 1997.59  855.326 2115.06  1431.33 2075.66  1975.34 1882.32
            2447.01 1549.37  2811.37 1101.52  3041.39 571.969  3120 0))
      (outline (path signal 100  3000 0  2918.99 -563.465  2682.51 -1081.28  2309.72 -1511.5
            1830.83 -1819.26  1284.63 -1979.64  715.37 -1979.64  169.17 -1819.26
            -309.721 -1511.5  -682.507 -1081.28  -918.986 -563.465  -1000 0
            -918.986 563.465  -682.507 1081.28  -309.721 1511.5  169.17 1819.26
            715.37 1979.64  1284.63 1979.64  1830.83 1819.26  2309.72 1511.5
            2682.51 1081.28  2918.99 563.465  3000 0))
      (pin Rect[A]Pad_1200x1200_um 1 0 0)
      (pin Round[A]Pad_1200_um 2 2000 0)
    )
    (image Capacitor_THT:CP_Radial_D4.0mm_P2.00mm::1
      (outline (path signal 100  3000 0  2918.99 -563.465  2682.51 -1081.28  2309.72 -1511.5
            1830.83 -1819.26  1284.63 -1979.64  715.37 -1979.64  169.17 -1819.26
            -309.721 -1511.5  -682.507 -1081.28  -918.986 -563.465  -1000 0
            -918.986 563.465  -682.507 1081.28  -309.721 1511.5  169.17 1819.26
            715.37 1979.64  1284.63 1979.64  1830.83 1819.26  2309.72 1511.5
            2682.51 1081.28  2918.99 563.465  3000 0))
      (outline (path signal 120  3120 0  3041.39 -571.969  2811.37 -1101.52  2447.01 -1549.37
            1975.34 -1882.32  1431.33 -2075.66  855.326 -2115.06  290.055 -1997.59
            -222.562 -1731.98  -644.508 -1337.91  -944.488 -844.61  -1100.25 -288.673
            -1100.25 288.673  -944.488 844.61  -644.508 1337.91  -222.562 1731.98
            290.055 1997.59  855.326 2115.06  1431.33 2075.66  1975.34 1882.32
            2447.01 1549.37  2811.37 1101.52  3041.39 571.969  3120 0))
      (outline (path signal 50  3250 0  3173.33 -582.343  2948.56 -1125  2590.99 -1590.99
            2125 -1948.56  1582.34 -2173.33  1000 -2250  417.657 -2173.33
            -125 -1948.56  -590.99 -1590.99  -948.557 -1125  -1173.33 -582.343
            -1250 0  -1173.33 582.343  -948.557 1125  -590.99 1590.99  -125 1948.56
            417.657 2173.33  1000 2250  1582.34 2173.33  2125 1948.56  2590.99 1590.99
            2948.56 1125  3173.33 582.343  3250 0))
      (outline (path signal 100  -702.554 867.5  -302.554 867.5))
      (outline (path signal 100  -502.554 1067.5  -502.554 667.5))
      (outline (path signal 120  1000 2080  1000 -2080))
      (outline (path signal 120  1040 2080  1040 -2080))
      (outline (path signal 120  1080 2079  1080 -2079))
      (outline (path signal 120  1120 2077  1120 -2077))
      (outline (path signal 120  1160 2074  1160 -2074))
      (outline (path signal 120  1200 2071  1200 840))
      (outline (path signal 120  1200 -840  1200 -2071))
      (outline (path signal 120  1240 2067  1240 840))
      (outline (path signal 120  1240 -840  1240 -2067))
      (outline (path signal 120  1280 2062  1280 840))
      (outline (path signal 120  1280 -840  1280 -2062))
      (outline (path signal 120  1320 2056  1320 840))
      (outline (path signal 120  1320 -840  1320 -2056))
      (outline (path signal 120  1360 2050  1360 840))
      (outline (path signal 120  1360 -840  1360 -2050))
      (outline (path signal 120  1400 2042  1400 840))
      (outline (path signal 120  1400 -840  1400 -2042))
      (outline (path signal 120  1440 2034  1440 840))
      (outline (path signal 120  1440 -840  1440 -2034))
      (outline (path signal 120  1480 2025  1480 840))
      (outline (path signal 120  1480 -840  1480 -2025))
      (outline (path signal 120  1520 2016  1520 840))
      (outline (path signal 120  1520 -840  1520 -2016))
      (outline (path signal 120  1560 2005  1560 840))
      (outline (path signal 120  1560 -840  1560 -2005))
      (outline (path signal 120  1600 1994  1600 840))
      (outline (path signal 120  1600 -840  1600 -1994))
      (outline (path signal 120  1640 1982  1640 840))
      (outline (path signal 120  1640 -840  1640 -1982))
      (outline (path signal 120  1680 1968  1680 840))
      (outline (path signal 120  1680 -840  1680 -1968))
      (outline (path signal 120  1721 1954  1721 840))
      (outline (path signal 120  1721 -840  1721 -1954))
      (outline (path signal 120  1761 1940  1761 840))
      (outline (path signal 120  1761 -840  1761 -1940))
      (outline (path signal 120  1801 1924  1801 840))
      (outline (path signal 120  1801 -840  1801 -1924))
      (outline (path signal 120  1841 1907  1841 840))
      (outline (path signal 120  1841 -840  1841 -1907))
      (outline (path signal 120  1881 1889  1881 840))
      (outline (path signal 120  1881 -840  1881 -1889))
      (outline (path signal 120  1921 1870  1921 840))
      (outline (path signal 120  1921 -840  1921 -1870))
      (outline (path signal 120  1961 1851  1961 840))
      (outline (path signal 120  1961 -840  1961 -1851))
      (outline (path signal 120  2001 1830  2001 840))
      (outline (path signal 120  2001 -840  2001 -1830))
      (outline (path signal 120  2041 1808  2041 840))
      (outline (path signal 120  2041 -840  2041 -1808))
      (outline (path signal 120  2081 1785  2081 840))
      (outline (path signal 120  2081 -840  2081 -1785))
      (outline (path signal 120  2121 1760  2121 840))
      (outline (path signal 120  2121 -840  2121 -1760))
      (outline (path signal 120  2161 1735  2161 840))
      (outline (path signal 120  2161 -840  2161 -1735))
      (outline (path signal 120  2201 1708  2201 840))
      (outline (path signal 120  2201 -840  2201 -1708))
      (outline (path signal 120  2241 1680  2241 840))
      (outline (path signal 120  2241 -840  2241 -1680))
      (outline (path signal 120  2281 1650  2281 840))
      (outline (path signal 120  2281 -840  2281 -1650))
      (outline (path signal 120  2321 1619  2321 840))
      (outline (path signal 120  2321 -840  2321 -1619))
      (outline (path signal 120  2361 1587  2361 840))
      (outline (path signal 120  2361 -840  2361 -1587))
      (outline (path signal 120  2401 1552  2401 840))
      (outline (path signal 120  2401 -840  2401 -1552))
      (outline (path signal 120  2441 1516  2441 840))
      (outline (path signal 120  2441 -840  2441 -1516))
      (outline (path signal 120  2481 1478  2481 840))
      (outline (path signal 120  2481 -840  2481 -1478))
      (outline (path signal 120  2521 1438  2521 840))
      (outline (path signal 120  2521 -840  2521 -1438))
      (outline (path signal 120  2561 1396  2561 840))
      (outline (path signal 120  2561 -840  2561 -1396))
      (outline (path signal 120  2601 1351  2601 840))
      (outline (path signal 120  2601 -840  2601 -1351))
      (outline (path signal 120  2641 1304  2641 840))
      (outline (path signal 120  2641 -840  2641 -1304))
      (outline (path signal 120  2681 1254  2681 840))
      (outline (path signal 120  2681 -840  2681 -1254))
      (outline (path signal 120  2721 1200  2721 840))
      (outline (path signal 120  2721 -840  2721 -1200))
      (outline (path signal 120  2761 1142  2761 840))
      (outline (path signal 120  2761 -840  2761 -1142))
      (outline (path signal 120  2801 1080  2801 840))
      (outline (path signal 120  2801 -840  2801 -1080))
      (outline (path signal 120  2841 1013  2841 -1013))
      (outline (path signal 120  2881 940  2881 -940))
      (outline (path signal 120  2921 859  2921 -859))
      (outline (path signal 120  2961 768  2961 -768))
      (outline (path signal 120  3001 664  3001 -664))
      (outline (path signal 120  3041 537  3041 -537))
      (outline (path signal 120  3081 370  3081 -370))
      (outline (path signal 120  -1269.8 1195  -869.801 1195))
      (outline (path signal 120  -1069.8 1395  -1069.8 995))
      (pin Round[A]Pad_1200_um 2 2000 0)
      (pin Rect[A]Pad_1200x1200_um 1 0 0)
    )
    (image "Package_TO_SOT_THT:TO-220-3_Vertical"
      (outline (path signal 50  7790 3400  -2710 3400))
      (outline (path signal 50  7790 -1510  7790 3400))
      (outline (path signal 50  -2710 -1510  7790 -1510))
      (outline (path signal 50  -2710 3400  -2710 -1510))
      (outline (path signal 120  4391 3270  4391 1760))
      (outline (path signal 120  690 3270  690 1760))
      (outline (path signal 120  -2580 1760  7660 1760))
      (outline (path signal 120  7660 3270  7660 -1371))
      (outline (path signal 120  -2580 3270  -2580 -1371))
      (outline (path signal 120  -2580 -1371  7660 -1371))
      (outline (path signal 120  -2580 3270  7660 3270))
      (outline (path signal 100  4390 3150  4390 1880))
      (outline (path signal 100  690 3150  690 1880))
      (outline (path signal 100  -2460 1880  7540 1880))
      (outline (path signal 100  7540 3150  -2460 3150))
      (outline (path signal 100  7540 -1250  7540 3150))
      (outline (path signal 100  -2460 -1250  7540 -1250))
      (outline (path signal 100  -2460 3150  -2460 -1250))
      (pin Rect[A]Pad_1905x2000_um 1 0 0)
      (pin Oval[A]Pad_1905x2000_um 2 2540 0)
      (pin Oval[A]Pad_1905x2000_um 3 5080 0)
    )
    (image Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal
      (outline (path signal 50  8670 1500  -1050 1500))
      (outline (path signal 50  8670 -1500  8670 1500))
      (outline (path signal 50  -1050 -1500  8670 -1500))
      (outline (path signal 50  -1050 1500  -1050 -1500))
      (outline (path signal 120  7080 -1370  7080 -1040))
      (outline (path signal 120  540 -1370  7080 -1370))
      (outline (path signal 120  540 -1040  540 -1370))
      (outline (path signal 120  7080 1370  7080 1040))
      (outline (path signal 120  540 1370  7080 1370))
      (outline (path signal 120  540 1040  540 1370))
      (outline (path signal 100  7620 0  6960 0))
      (outline (path signal 100  0 0  660 0))
      (outline (path signal 100  6960 1250  660 1250))
      (outline (path signal 100  6960 -1250  6960 1250))
      (outline (path signal 100  660 -1250  6960 -1250))
      (outline (path signal 100  660 1250  660 -1250))
      (pin Round[A]Pad_1600_um 1 0 0)
      (pin Oval[A]Pad_1600x1600_um 2 7620 0)
    )
    (image Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical
      (outline (path signal 50  1800 1800  -1800 1800))
      (outline (path signal 50  1800 -4350  1800 1800))
      (outline (path signal 50  -1800 -4350  1800 -4350))
      (outline (path signal 50  -1800 1800  -1800 -4350))
      (outline (path signal 120  -1330 1330  0 1330))
      (outline (path signal 120  -1330 0  -1330 1330))
      (outline (path signal 120  -1330 -1270  1330 -1270))
      (outline (path signal 120  1330 -1270  1330 -3870))
      (outline (path signal 120  -1330 -1270  -1330 -3870))
      (outline (path signal 120  -1330 -3870  1330 -3870))
      (outline (path signal 100  -1270 635  -635 1270))
      (outline (path signal 100  -1270 -3810  -1270 635))
      (outline (path signal 100  1270 -3810  -1270 -3810))
      (outline (path signal 100  1270 1270  1270 -3810))
      (outline (path signal 100  -635 1270  1270 1270))
      (pin Rect[A]Pad_1700x1700_um 1 0 0)
      (pin Oval[A]Pad_1700x1700_um 2 0 -2540)
    )
    (image st1:ST1DC12VF
      (outline (path signal 200  -3500 0  -3500 0))
      (outline (path signal 200  -3300 0  -3300 0))
      (outline (path signal 100  -3800 13080  -3800 -2920))
      (outline (path signal 100  29200 13080  -3800 13080))
      (outline (path signal 100  29200 -2920  29200 13080))
      (outline (path signal 100  -3800 -2920  29200 -2920))
      (outline (path signal 100  -2800 12080  -2800 -1920))
      (outline (path signal 100  28200 12080  -2800 12080))
      (outline (path signal 100  28200 -1920  28200 12080))
      (outline (path signal 100  -2800 -1920  28200 -1920))
      (outline (path signal 200  -2800 12080  -2800 -1920))
      (outline (path signal 200  28200 12080  -2800 12080))
      (outline (path signal 200  28200 -1920  28200 12080))
      (outline (path signal 200  -2800 -1920  28200 -1920))
      (pin Round[A]Pad_2250_um 1 0 0)
      (pin Round[A]Pad_2250_um 4 25400 0)
      (pin Round[A]Pad_2250_um 5 25400 10160)
      (pin Round[A]Pad_2250_um 6 17780 10160)
      (pin Round[A]Pad_2250_um 7 7620 10160)
      (pin Round[A]Pad_2250_um 8 200 10160)
    )
    (image st1:ST1DC12VF::1
      (outline (path signal 200  -2800 -1920  28200 -1920))
      (outline (path signal 200  28200 -1920  28200 12080))
      (outline (path signal 200  28200 12080  -2800 12080))
      (outline (path signal 200  -2800 12080  -2800 -1920))
      (outline (path signal 100  -2800 -1920  28200 -1920))
      (outline (path signal 100  28200 -1920  28200 12080))
      (outline (path signal 100  28200 12080  -2800 12080))
      (outline (path signal 100  -2800 12080  -2800 -1920))
      (outline (path signal 100  -3800 -2920  29200 -2920))
      (outline (path signal 100  29200 -2920  29200 13080))
      (outline (path signal 100  29200 13080  -3800 13080))
      (outline (path signal 100  -3800 13080  -3800 -2920))
      (outline (path signal 200  -3300 0  -3300 0))
      (outline (path signal 200  -3500 0  -3500 0))
      (pin Round[A]Pad_2250_um 8 200 10160)
      (pin Round[A]Pad_2250_um 7 7620 10160)
      (pin Round[A]Pad_2250_um 6 17780 10160)
      (pin Round[A]Pad_2250_um 5 25400 10160)
      (pin Round[A]Pad_2250_um 4 25400 0)
      (pin Round[A]Pad_2250_um 1 0 0)
    )
    (padstack Round[A]Pad_1200_um
      (shape (circle F.Cu 1200))
      (shape (circle B.Cu 1200))
      (attach off)
    )
    (padstack Round[A]Pad_1600_um
      (shape (circle F.Cu 1600))
      (shape (circle B.Cu 1600))
      (attach off)
    )
    (padstack Round[A]Pad_2100_um
      (shape (circle F.Cu 2100))
      (shape (circle B.Cu 2100))
      (attach off)
    )
    (padstack Round[A]Pad_2250_um
      (shape (circle F.Cu 2250))
      (shape (circle B.Cu 2250))
      (attach off)
    )
    (padstack Round[A]Pad_4000_um
      (shape (circle F.Cu 4000))
      (shape (circle B.Cu 4000))
      (attach off)
    )
    (padstack Round[A]Pad_5600_um
      (shape (circle F.Cu 5600))
      (shape (circle B.Cu 5600))
      (attach off)
    )
    (padstack Oval[A]Pad_1600x1600_um
      (shape (path F.Cu 1600  0 0  0 0))
      (shape (path B.Cu 1600  0 0  0 0))
      (attach off)
    )
    (padstack Oval[A]Pad_1700x1700_um
      (shape (path F.Cu 1700  0 0  0 0))
      (shape (path B.Cu 1700  0 0  0 0))
      (attach off)
    )
    (padstack Oval[A]Pad_1905x2000_um
      (shape (path F.Cu 1905  0 -47.5  0 47.5))
      (shape (path B.Cu 1905  0 -47.5  0 47.5))
      (attach off)
    )
    (padstack RoundRect[A]Pad_2100x2100_250.95_um
      (shape (polygon F.Cu 0  843.578 1047.14  885.831 1035.82  925.476 1017.33  961.309 992.24
            992.24 961.309  1017.33 925.476  1035.82 885.831  1047.14 843.578
            1050.95 800.001  1050.95 -800.001  1047.14 -843.578  1035.82 -885.831
            1017.33 -925.476  992.24 -961.309  961.309 -992.24  925.476 -1017.33
            885.831 -1035.82  843.578 -1047.14  800.001 -1050.95  -800.001 -1050.95
            -843.578 -1047.14  -885.831 -1035.82  -925.476 -1017.33  -961.309 -992.24
            -992.24 -961.309  -1017.33 -925.476  -1035.82 -885.831  -1047.14 -843.578
            -1050.95 -800.001  -1050.95 800.001  -1047.14 843.578  -1035.82 885.831
            -1017.33 925.476  -992.24 961.309  -961.309 992.24  -925.476 1017.33
            -885.831 1035.82  -843.578 1047.14  -800.001 1050.95  800.001 1050.95
            843.578 1047.14))
      (shape (polygon B.Cu 0  843.578 1047.14  885.831 1035.82  925.476 1017.33  961.309 992.24
            992.24 961.309  1017.33 925.476  1035.82 885.831  1047.14 843.578
            1050.95 800.001  1050.95 -800.001  1047.14 -843.578  1035.82 -885.831
            1017.33 -925.476  992.24 -961.309  961.309 -992.24  925.476 -1017.33
            885.831 -1035.82  843.578 -1047.14  800.001 -1050.95  -800.001 -1050.95
            -843.578 -1047.14  -885.831 -1035.82  -925.476 -1017.33  -961.309 -992.24
            -992.24 -961.309  -1017.33 -925.476  -1035.82 -885.831  -1047.14 -843.578
            -1050.95 -800.001  -1050.95 800.001  -1047.14 843.578  -1035.82 885.831
            -1017.33 925.476  -992.24 961.309  -961.309 992.24  -925.476 1017.33
            -885.831 1035.82  -843.578 1047.14  -800.001 1050.95  800.001 1050.95
            843.578 1047.14))
      (attach off)
    )
    (padstack Rect[A]Pad_1200x1200_um
      (shape (rect F.Cu -600 -600 600 600))
      (shape (rect B.Cu -600 -600 600 600))
      (attach off)
    )
    (padstack Rect[A]Pad_1600x1600_um
      (shape (rect F.Cu -800 -800 800 800))
      (shape (rect B.Cu -800 -800 800 800))
      (attach off)
    )
    (padstack Rect[A]Pad_1700x1700_um
      (shape (rect F.Cu -850 -850 850 850))
      (shape (rect B.Cu -850 -850 850 850))
      (attach off)
    )
    (padstack Rect[A]Pad_1905x2000_um
      (shape (rect F.Cu -952.5 -1000 952.5 1000))
      (shape (rect B.Cu -952.5 -1000 952.5 1000))
      (attach off)
    )
    (padstack "Via[0-1]_800:400_um"
      (shape (circle F.Cu 800))
      (shape (circle B.Cu 800))
      (attach off)
    )
    (padstack "Via[0-1]_1000:400_um"
      (shape (circle F.Cu 1000))
      (shape (circle B.Cu 1000))
      (attach off)
    )
    (padstack "Via[0-1]_1500:400_um"
      (shape (circle F.Cu 1500))
      (shape (circle B.Cu 1500))
      (attach off)
    )
  )
  (network
    (net GND
      (pins J_IN3-2 J_OUT1-2 J_IN2-2 U1-8 J_OUT3-2 J_IN1-2 A1-29 A1-4 J1-2 J2-3 J_OUT2-2
        C1-2 C2-2 U2-2 R1-2)
    )
    (net "Net-(A1-Pad11)"
      (pins U1-1 A1-11)
    )
    (net "Net-(A1-Pad10)"
      (pins U1-2 A1-10)
    )
    (net "Net-(A1-Pad9)"
      (pins U1-3 A1-9)
    )
    (net "Net-(A1-Pad8)"
      (pins U1-4 A1-8)
    )
    (net "Net-(A1-Pad7)"
      (pins U1-5 A1-7)
    )
    (net "Net-(A1-Pad6)"
      (pins U1-6 A1-6)
    )
    (net "Net-(J_IN1-Pad1)"
      (pins J_IN1-1 K1-6 K1-7)
    )
    (net "Net-(J_IN2-Pad1)"
      (pins J_IN2-1 K3-7 K3-6)
    )
    (net "Net-(J_IN3-Pad1)"
      (pins J_IN3-1 K5-7 K5-6)
    )
    (net "Net-(J_OUT1-Pad1)"
      (pins J_OUT1-1 K1-5 K4-5 K6-8)
    )
    (net "Net-(J_OUT2-Pad1)"
      (pins J_OUT2-1 K2-5 K3-5 K6-5)
    )
    (net "Net-(J_OUT3-Pad1)"
      (pins J_OUT3-1 K2-8 K4-8 K5-5)
    )
    (net "Net-(K1-Pad8)"
      (pins K1-8 K2-6 K2-7)
    )
    (net "Net-(K3-Pad8)"
      (pins K3-8 K4-6 K4-7)
    )
    (net "Net-(K5-Pad8)"
      (pins K5-8 K6-7 K6-6)
    )
    (net VCC
      (pins U1-9 J1-1 C1-1 U2-1 K1-4 K2-4 K3-4 K4-4 K5-4 K6-4)
    )
    (net "Net-(A1-Pad27)"
      (pins A1-27 J2-4 C2-1 U2-3 SW1-1)
    )
    (net "Net-(A1-Pad24)"
      (pins A1-24 J2-2)
    )
    (net "Net-(A1-Pad23)"
      (pins A1-23 J2-1)
    )
    (net "Net-(K1-Pad1)"
      (pins U1-16 K1-1)
    )
    (net "Net-(K2-Pad1)"
      (pins U1-15 K2-1)
    )
    (net "Net-(K3-Pad1)"
      (pins U1-14 K3-1)
    )
    (net "Net-(K4-Pad1)"
      (pins U1-13 K4-1)
    )
    (net "Net-(K5-Pad1)"
      (pins U1-12 K5-1)
    )
    (net "Net-(K6-Pad1)"
      (pins U1-11 K6-1)
    )
    (net "Net-(A1-Pad5)"
      (pins A1-5 R1-1 SW1-2)
    )
    (class kicad_default "" "Net-(A1-Pad23)" "Net-(A1-Pad24)" "Net-(A1-Pad27)"
      "Net-(A1-Pad5)" "Net-(K1-Pad1)" "Net-(K2-Pad1)" "Net-(K3-Pad1)" "Net-(K4-Pad1)"
      "Net-(K5-Pad1)" "Net-(K6-Pad1)" VCC
      (circuit
        (use_via Via[0-1]_800:400_um)
      )
      (rule
        (width 250)
        (clearance 400.1)
      )
    )
    (class gnd GND
      (circuit
        (use_via Via[0-1]_1000:400_um)
      )
      (rule
        (width 1000)
        (clearance 400.1)
      )
    )
    (class logic_signal "Net-(A1-Pad10)" "Net-(A1-Pad11)" "Net-(A1-Pad6)"
      "Net-(A1-Pad7)" "Net-(A1-Pad8)" "Net-(A1-Pad9)"
      (circuit
        (use_via Via[0-1]_800:400_um)
      )
      (rule
        (width 250)
        (clearance 400.1)
      )
    )
    (class power
      (circuit
        (use_via Via[0-1]_800:400_um)
      )
      (rule
        (width 250)
        (clearance 400.1)
      )
    )
    (class rf_signal "Net-(J_IN1-Pad1)" "Net-(J_IN2-Pad1)" "Net-(J_IN3-Pad1)"
      "Net-(J_OUT1-Pad1)" "Net-(J_OUT2-Pad1)" "Net-(J_OUT3-Pad1)" "Net-(K1-Pad8)"
      "Net-(K3-Pad8)" "Net-(K5-Pad8)"
      (circuit
        (use_via Via[0-1]_1500:400_um)
      )
      (rule
        (width 1000)
        (clearance 1200.1)
      )
    )
  )
  (wiring
    (wire (path F.Cu 250  143096 -105662  143096 -111758)(net "Net-(A1-Pad11)")(type protect))
    (wire (path B.Cu 250  145636 -111758  145636 -112636)(net "Net-(A1-Pad10)")(type protect))
    (wire (path F.Cu 250  145636 -105662  145636 -111758)(net "Net-(A1-Pad10)")(type protect))
    (wire (path F.Cu 250  148176 -105662  148176 -111758)(net "Net-(A1-Pad9)")(type protect))
    (wire (path F.Cu 250  150716 -105662  150716 -111758)(net "Net-(A1-Pad8)")(type protect))
    (wire (path F.Cu 250  153256 -105662  153256 -111758)(net "Net-(A1-Pad7)")(type protect))
    (wire (path F.Cu 250  155796 -105662  155796 -111758)(net "Net-(A1-Pad6)")(type protect))
    (wire (path F.Cu 250  160876 -126998  160876 -131348  158336 -133888)(net "Net-(A1-Pad27)")(type protect))
    (wire (path F.Cu 250  192500 -119500  168374 -119500  160876 -126998)(net "Net-(A1-Pad27)")(type protect))
    (wire (path F.Cu 250  200000 -119500  192500 -119500)(net "Net-(A1-Pad27)")(type protect))
    (wire (path F.Cu 250  180000 -107000  192500 -119500)(net "Net-(A1-Pad27)")(type protect))
    (wire (path F.Cu 250  206080 -112300  206080 -113420  200000 -119500)(net "Net-(A1-Pad27)")(type protect))
    (wire (path F.Cu 250  153256 -126998  153256 -133888)(net "Net-(A1-Pad24)")(type protect))
    (wire (path F.Cu 250  150716 -133888  150716 -126998)(net "Net-(A1-Pad23)")(type protect))
    (wire (path F.Cu 250  187500 -104500  180040 -104500  180000 -104460  165634 -104460
            158336 -111758)(net "Net-(A1-Pad5)")(type protect))
  )
)