(pcb /home/ixyd/Nextcloud/funkstuff/projects/antennaswitch/first_try/first_try.dsn
  (parser
    (string_quote ")
    (space_in_quoted_tokens on)
    (host_cad "KiCad's Pcbnew")
    (host_version "5.1.8+dfsg1-1+b1")
  )
  (resolution um 10)
  (unit um)
  (structure
    (layer F.Cu
      (type signal)
      (property
        (index 0)
      )
    )
    (layer B.Cu
      (type signal)
      (property
        (index 1)
      )
    )
    (boundary
      (path pcb 0  227000 -125000  51000 -125000  51000 -23000  227000 -23000
            227000 -125000)
    )
    (plane GND (polygon F.Cu 0  227000 -125000  51000 -125000  51000 -23000  227000 -23000
            227000 -125000))
    (plane GND (polygon B.Cu 0  227000 -125000  51000 -125000  51000 -23000  227000 -23000
            227000 -125000))
    (via "Via[0-1]_800:400_um")
    (rule
      (width 250)
      (clearance 400.1)
      (clearance 400.1 (type default_smd))
      (clearance 100 (type smd_smd))
    )
  )
  (placement
    (component first_try:my_pl_socket
      (place J_IN3 125000 -30000 front 0 (PN Conn_Coaxial))
      (place J_OUT1 155000 -30000 front 0 (PN Conn_Coaxial))
      (place J_IN2 95000 -30000 front 0 (PN Conn_Coaxial))
      (place J_OUT3 215000 -30000 front 0 (PN Conn_Coaxial))
      (place J_OUT2 185000 -30000 front 0 (PN Conn_Coaxial))
      (place J_IN1 65000 -30000 front 0 (PN Conn_Coaxial))
    )
    (component first_try:ST1DC12VF
      (place K3 118000 -47000 front 270 (PN "ST1-DC12V-F"))
      (place K4 148000 -47000 front 270 (PN "ST1-DC12V-F"))
      (place K6 207000 -47000 front 270 (PN "ST1-DC12V-F"))
      (place K1 57000 -47000 front 270 (PN "ST1-DC12V-F"))
      (place K5 178000 -47000 front 270 (PN "ST1-DC12V-F"))
      (place K2 88000 -47000 front 270 (PN "ST1-DC12V-F"))
    )
    (component Connector:Banana_Jack_2Pin
      (place J1 207000 -105000 front 180 (PN Conn_01x02_Male))
    )
    (component "Package_DIP:DIP-16_W7.62mm_Socket"
      (place U1 127550 -90800 front 90 (PN ULN2003A))
    )
    (component Module:Arduino_Nano
      (place A1 152950 -97120 front 270 (PN Arduino_Nano_Every))
    )
  )
  (library
    (image first_try:my_pl_socket
      (outline (path signal 120  11430 -5080  11430 6350))
      (outline (path signal 120  11430 6350  -12700 6350))
      (outline (path signal 120  -12700 6350  -12700 -5080))
      (outline (path signal 120  -12700 -5080  11430 -5080))
      (pin Round[A]Pad_4000_um 2 -8890 0)
      (pin Round[A]Pad_4000_um 1 0 0)
    )
    (image first_try:ST1DC12VF
      (outline (path signal 200  -2800 -3190  28200 -3190))
      (outline (path signal 200  28200 -3190  28200 10810))
      (outline (path signal 200  28200 10810  -2800 10810))
      (outline (path signal 200  -2800 10810  -2800 -3190))
      (outline (path signal 100  -2800 -3190  28200 -3190))
      (outline (path signal 100  28200 -3190  28200 10810))
      (outline (path signal 100  28200 10810  -2800 10810))
      (outline (path signal 100  -2800 10810  -2800 -3190))
      (outline (path signal 100  -3800 -4190  29200 -4190))
      (outline (path signal 100  29200 -4190  29200 11810))
      (outline (path signal 100  29200 11810  -3800 11810))
      (outline (path signal 100  -3800 11810  -3800 -4190))
      (outline (path signal 200  -3300 0  -3300 0))
      (outline (path signal 200  -3500 0  -3500 0))
      (pin Round[A]Pad_2250_um 1 0 0)
      (pin Round[A]Pad_2250_um 4 25400 0)
      (pin Round[A]Pad_2250_um 5 25400 7620)
      (pin Round[A]Pad_2250_um 6 17780 7620)
      (pin Round[A]Pad_2250_um 7 7620 7620)
      (pin Round[A]Pad_2250_um 8 200 7620)
    )
    (image Connector:Banana_Jack_2Pin
      (outline (path signal 50  30000 5500  0 5500))
      (outline (path signal 50  0 -5500  30000 -5500))
      (outline (path signal 120  0 -5250  30000 -5250))
      (outline (path signal 120  30000 5250  0 5250))
      (outline (path signal 100  32000 0  31919 -563.465  31682.5 -1081.28  31309.7 -1511.5
            30830.8 -1819.26  30284.6 -1979.64  29715.4 -1979.64  29169.2 -1819.26
            28690.3 -1511.5  28317.5 -1081.28  28081 -563.465  28000 0  28081 563.465
            28317.5 1081.28  28690.3 1511.5  29169.2 1819.26  29715.4 1979.64
            30284.6 1979.64  30830.8 1819.26  31309.7 1511.5  31682.5 1081.28
            31919 563.465  32000 0))
      (outline (path signal 100  2000 0  1918.99 -563.465  1682.51 -1081.28  1309.72 -1511.5
            830.83 -1819.26  284.63 -1979.64  -284.63 -1979.64  -830.83 -1819.26
            -1309.72 -1511.5  -1682.51 -1081.28  -1918.99 -563.465  -2000 0
            -1918.99 563.465  -1682.51 1081.28  -1309.72 1511.5  -830.83 1819.26
            -284.63 1979.64  284.63 1979.64  830.83 1819.26  1309.72 1511.5
            1682.51 1081.28  1918.99 563.465  2000 0))
      (outline (path signal 100  4750 0  4669.12 -872.81  4429.24 -1715.9  4038.53 -2500.55
            3510.29 -3200.05  2862.51 -3790.58  2117.26 -4252.03  1299.9 -4568.67
            438.275 -4729.74  -438.275 -4729.74  -1299.9 -4568.67  -2117.26 -4252.03
            -2862.51 -3790.58  -3510.29 -3200.05  -4038.53 -2500.55  -4429.24 -1715.9
            -4669.12 -872.81  -4750 0  -4669.12 872.81  -4429.24 1715.9
            -4038.53 2500.55  -3510.29 3200.05  -2862.51 3790.58  -2117.26 4252.03
            -1299.9 4568.67  -438.275 4729.74  438.275 4729.74  1299.9 4568.67
            2117.26 4252.03  2862.51 3790.58  3510.29 3200.05  4038.53 2500.55
            4429.24 1715.9  4669.12 872.81  4750 0))
      (outline (path signal 100  34750 0  34669.1 -872.81  34429.2 -1715.9  34038.5 -2500.55
            33510.3 -3200.05  32862.5 -3790.58  32117.3 -4252.03  31299.9 -4568.67
            30438.3 -4729.74  29561.7 -4729.74  28700.1 -4568.67  27882.7 -4252.03
            27137.5 -3790.58  26489.7 -3200.05  25961.5 -2500.55  25570.8 -1715.9
            25330.9 -872.81  25250 0  25330.9 872.81  25570.8 1715.9  25961.5 2500.55
            26489.7 3200.05  27137.5 3790.58  27882.7 4252.03  28700.1 4568.67
            29561.7 4729.74  30438.3 4729.74  31299.9 4568.67  32117.3 4252.03
            32862.5 3790.58  33510.3 3200.05  34038.5 2500.55  34429.2 1715.9
            34669.1 872.81  34750 0))
      (pin Round[A]Pad_10160_um 2 29970 0)
      (pin Round[A]Pad_10160_um 1 0 0)
    )
    (image "Package_DIP:DIP-16_W7.62mm_Socket"
      (outline (path signal 100  1635 1270  6985 1270))
      (outline (path signal 100  6985 1270  6985 -19050))
      (outline (path signal 100  6985 -19050  635 -19050))
      (outline (path signal 100  635 -19050  635 270))
      (outline (path signal 100  635 270  1635 1270))
      (outline (path signal 100  -1270 1330  -1270 -19110))
      (outline (path signal 100  -1270 -19110  8890 -19110))
      (outline (path signal 100  8890 -19110  8890 1330))
      (outline (path signal 100  8890 1330  -1270 1330))
      (outline (path signal 120  2810 1330  1160 1330))
      (outline (path signal 120  1160 1330  1160 -19110))
      (outline (path signal 120  1160 -19110  6460 -19110))
      (outline (path signal 120  6460 -19110  6460 1330))
      (outline (path signal 120  6460 1330  4810 1330))
      (outline (path signal 120  -1330 1390  -1330 -19170))
      (outline (path signal 120  -1330 -19170  8950 -19170))
      (outline (path signal 120  8950 -19170  8950 1390))
      (outline (path signal 120  8950 1390  -1330 1390))
      (outline (path signal 50  -1550 1600  -1550 -19400))
      (outline (path signal 50  -1550 -19400  9150 -19400))
      (outline (path signal 50  9150 -19400  9150 1600))
      (outline (path signal 50  9150 1600  -1550 1600))
      (pin Oval[A]Pad_1600x1600_um 16 7620 0)
      (pin Oval[A]Pad_1600x1600_um 8 0 -17780)
      (pin Oval[A]Pad_1600x1600_um 15 7620 -2540)
      (pin Oval[A]Pad_1600x1600_um 7 0 -15240)
      (pin Oval[A]Pad_1600x1600_um 14 7620 -5080)
      (pin Oval[A]Pad_1600x1600_um 6 0 -12700)
      (pin Oval[A]Pad_1600x1600_um 13 7620 -7620)
      (pin Oval[A]Pad_1600x1600_um 5 0 -10160)
      (pin Oval[A]Pad_1600x1600_um 12 7620 -10160)
      (pin Oval[A]Pad_1600x1600_um 4 0 -7620)
      (pin Oval[A]Pad_1600x1600_um 11 7620 -12700)
      (pin Oval[A]Pad_1600x1600_um 3 0 -5080)
      (pin Oval[A]Pad_1600x1600_um 10 7620 -15240)
      (pin Oval[A]Pad_1600x1600_um 2 0 -2540)
      (pin Oval[A]Pad_1600x1600_um 9 7620 -17780)
      (pin Rect[A]Pad_1600x1600_um 1 0 0)
    )
    (image Module:Arduino_Nano
      (outline (path signal 120  1270 -1270  1270 1270))
      (outline (path signal 120  1270 1270  -1400 1270))
      (outline (path signal 120  -1400 -1270  -1400 -39500))
      (outline (path signal 120  -1400 3940  -1400 1270))
      (outline (path signal 120  13970 1270  16640 1270))
      (outline (path signal 120  13970 1270  13970 -36830))
      (outline (path signal 120  13970 -36830  16640 -36830))
      (outline (path signal 120  1270 -1270  -1400 -1270))
      (outline (path signal 120  1270 -1270  1270 -36830))
      (outline (path signal 120  1270 -36830  -1400 -36830))
      (outline (path signal 100  3810 -31750  11430 -31750))
      (outline (path signal 100  11430 -31750  11430 -41910))
      (outline (path signal 100  11430 -41910  3810 -41910))
      (outline (path signal 100  3810 -41910  3810 -31750))
      (outline (path signal 120  -1400 -39500  16640 -39500))
      (outline (path signal 120  16640 -39500  16640 3940))
      (outline (path signal 120  16640 3940  -1400 3940))
      (outline (path signal 100  16510 -39370  -1270 -39370))
      (outline (path signal 100  -1270 -39370  -1270 2540))
      (outline (path signal 100  -1270 2540  0 3810))
      (outline (path signal 100  0 3810  16510 3810))
      (outline (path signal 100  16510 3810  16510 -39370))
      (outline (path signal 50  -1530 4060  16750 4060))
      (outline (path signal 50  -1530 4060  -1530 -42160))
      (outline (path signal 50  16750 -42160  16750 4060))
      (outline (path signal 50  16750 -42160  -1530 -42160))
      (pin Oval[A]Pad_1600x1600_um 16 15240 -35560)
      (pin Oval[A]Pad_1600x1600_um 15 0 -35560)
      (pin Oval[A]Pad_1600x1600_um 30 15240 0)
      (pin Oval[A]Pad_1600x1600_um 14 0 -33020)
      (pin Oval[A]Pad_1600x1600_um 29 15240 -2540)
      (pin Oval[A]Pad_1600x1600_um 13 0 -30480)
      (pin Oval[A]Pad_1600x1600_um 28 15240 -5080)
      (pin Oval[A]Pad_1600x1600_um 12 0 -27940)
      (pin Oval[A]Pad_1600x1600_um 27 15240 -7620)
      (pin Oval[A]Pad_1600x1600_um 11 0 -25400)
      (pin Oval[A]Pad_1600x1600_um 26 15240 -10160)
      (pin Oval[A]Pad_1600x1600_um 10 0 -22860)
      (pin Oval[A]Pad_1600x1600_um 25 15240 -12700)
      (pin Oval[A]Pad_1600x1600_um 9 0 -20320)
      (pin Oval[A]Pad_1600x1600_um 24 15240 -15240)
      (pin Oval[A]Pad_1600x1600_um 8 0 -17780)
      (pin Oval[A]Pad_1600x1600_um 23 15240 -17780)
      (pin Oval[A]Pad_1600x1600_um 7 0 -15240)
      (pin Oval[A]Pad_1600x1600_um 22 15240 -20320)
      (pin Oval[A]Pad_1600x1600_um 6 0 -12700)
      (pin Oval[A]Pad_1600x1600_um 21 15240 -22860)
      (pin Oval[A]Pad_1600x1600_um 5 0 -10160)
      (pin Oval[A]Pad_1600x1600_um 20 15240 -25400)
      (pin Oval[A]Pad_1600x1600_um 4 0 -7620)
      (pin Oval[A]Pad_1600x1600_um 19 15240 -27940)
      (pin Oval[A]Pad_1600x1600_um 3 0 -5080)
      (pin Oval[A]Pad_1600x1600_um 18 15240 -30480)
      (pin Oval[A]Pad_1600x1600_um 2 0 -2540)
      (pin Oval[A]Pad_1600x1600_um 17 15240 -33020)
      (pin Rect[A]Pad_1600x1600_um 1 0 0)
    )
    (padstack Round[A]Pad_10160_um
      (shape (circle F.Cu 10160))
      (shape (circle B.Cu 10160))
      (attach off)
    )
    (padstack Round[A]Pad_2250_um
      (shape (circle F.Cu 2250))
      (shape (circle B.Cu 2250))
      (attach off)
    )
    (padstack Round[A]Pad_4000_um
      (shape (circle F.Cu 4000))
      (shape (circle B.Cu 4000))
      (attach off)
    )
    (padstack Oval[A]Pad_1600x1600_um
      (shape (path F.Cu 1600  0 0  0 0))
      (shape (path B.Cu 1600  0 0  0 0))
      (attach off)
    )
    (padstack Rect[A]Pad_1600x1600_um
      (shape (rect F.Cu -800 -800 800 800))
      (shape (rect B.Cu -800 -800 800 800))
      (attach off)
    )
    (padstack "Via[0-1]_800:400_um"
      (shape (circle F.Cu 800))
      (shape (circle B.Cu 800))
      (attach off)
    )
  )
  (network
    (net GND
      (pins J_IN3-2 J_OUT1-2 K3-1 J1-1 K4-1 K6-1 J_IN2-2 U1-8 K1-1 J_OUT3-2 J_OUT2-2
        J_IN1-2 K5-1 A1-29 A1-4 K2-1)
    )
    (net "Net-(A1-Pad11)"
      (pins U1-1 A1-11)
    )
    (net "Net-(A1-Pad10)"
      (pins U1-2 A1-10)
    )
    (net "Net-(A1-Pad9)"
      (pins U1-3 A1-9)
    )
    (net "Net-(A1-Pad8)"
      (pins U1-4 A1-8)
    )
    (net "Net-(K1-Pad4)"
      (pins U1-16 K1-4)
    )
    (net "Net-(K2-Pad4)"
      (pins U1-15 K2-4)
    )
    (net "Net-(K3-Pad4)"
      (pins K3-4 U1-14)
    )
    (net "Net-(K4-Pad4)"
      (pins K4-4 U1-13)
    )
    (net "Net-(K5-Pad4)"
      (pins U1-12 K5-4)
    )
    (net "Net-(K6-Pad4)"
      (pins K6-4 U1-11)
    )
    (net "Net-(A1-Pad7)"
      (pins U1-5 A1-7)
    )
    (net "Net-(A1-Pad6)"
      (pins U1-6 A1-6)
    )
    (net "Net-(J_IN1-Pad1)"
      (pins K1-6 K1-7 J_IN1-1)
    )
    (net "Net-(J_IN2-Pad1)"
      (pins K3-6 K3-7 J_IN2-1)
    )
    (net "Net-(J_IN3-Pad1)"
      (pins J_IN3-1 K5-6 K5-7)
    )
    (net "Net-(J_OUT1-Pad1)"
      (pins J_OUT1-1 K4-5 K6-8 K1-5)
    )
    (net "Net-(J_OUT2-Pad1)"
      (pins K3-5 K6-5 J_OUT2-1 K2-5)
    )
    (net "Net-(J_OUT3-Pad1)"
      (pins K4-8 J_OUT3-1 K5-5 K2-8)
    )
    (net "Net-(K1-Pad8)"
      (pins K1-8 K2-6 K2-7)
    )
    (net "Net-(K3-Pad8)"
      (pins K3-8 K4-6 K4-7)
    )
    (net "Net-(K5-Pad8)"
      (pins K6-6 K6-7 K5-8)
    )
    (net VCC
      (pins J1-2 U1-9 A1-30)
    )
    (class kicad_default "" VCC
      (circuit
        (use_via Via[0-1]_800:400_um)
      )
      (rule
        (width 250)
        (clearance 400.1)
      )
    )
    (class logic_signal "Net-(A1-Pad10)" "Net-(A1-Pad11)" "Net-(A1-Pad6)"
      "Net-(A1-Pad7)" "Net-(A1-Pad8)" "Net-(A1-Pad9)"
      (circuit
        (use_via Via[0-1]_800:400_um)
      )
      (rule
        (width 250)
        (clearance 400.1)
      )
    )
    (class power "Net-(K1-Pad4)" "Net-(K2-Pad4)" "Net-(K3-Pad4)" "Net-(K4-Pad4)"
      "Net-(K5-Pad4)" "Net-(K6-Pad4)"
      (circuit
        (use_via Via[0-1]_800:400_um)
      )
      (rule
        (width 250)
        (clearance 400.1)
      )
    )
    (class rf_signal GND "Net-(J_IN1-Pad1)" "Net-(J_IN2-Pad1)" "Net-(J_IN3-Pad1)"
      "Net-(J_OUT1-Pad1)" "Net-(J_OUT2-Pad1)" "Net-(J_OUT3-Pad1)" "Net-(K1-Pad8)"
      "Net-(K3-Pad8)" "Net-(K5-Pad8)"
      (circuit
        (use_via Via[0-1]_800:400_um)
      )
      (rule
        (width 1000)
        (clearance 400.1)
      )
    )
  )
  (wiring
    (wire (path B.Cu 250  127550 -97120  127550 -90800)(net "Net-(A1-Pad11)")(type protect))
    (wire (path B.Cu 250  130090 -97120  130090 -90800)(net "Net-(A1-Pad10)")(type protect))
    (wire (path B.Cu 250  132630 -97120  132630 -90800)(net "Net-(A1-Pad9)")(type protect))
    (wire (path B.Cu 250  135170 -97120  135170 -90800)(net "Net-(A1-Pad8)")(type protect))
    (wire (path B.Cu 250  137710 -97120  137710 -90800)(net "Net-(A1-Pad7)")(type protect))
    (wire (path B.Cu 250  140250 -97120  140250 -90800)(net "Net-(A1-Pad6)")(type protect))
    (wire (path F.Cu 250  152950 -112360  154275 -112360)(net VCC)(type protect))
    (wire (path F.Cu 250  161310 -105000  161310 -100485  145330 -84505.3)(net VCC)(type protect))
    (wire (path F.Cu 250  154275 -112360  154275 -112035  161310 -105000  177030 -105000)(net VCC)(type protect))
    (wire (path F.Cu 250  145330 -83180  145330 -84505.3)(net VCC)(type protect))
  )
)